Why does arm use indirect addressing

The address of the operand is obtained by adding to the contents of the general register called index register a constant value. The number of the index register and the constant value are included in the instruction code. Index Mode is used to access an array whose elements are in successive memory locations. The content of the instruction code, represents the starting address of the array and the value of the index register, and the index value of the current element.

By incrementing or decrementing index register different element of the array can be accessed. The effective address of the operand is the contents of a register or main memory location, location whose address appears in the instruction.

Indirection is noted by placing the name of the register or the memory address given in the instruction in parentheses. The variants of these addressing schemes, and the allowable immediate values, differ between instructions. You need to read the description of each instruction to know what it supports. Section This is called post-indexed because the update occurs after the dereference. It corresponds roughly to the C postincrement operator. If you use pre-indexing or post-indexing, then the base register cannot be the register being loaded or stored.

Some special rules kick in if the base register is pc. First of all, you cannot use pre-indexing or post-indexing with pc. Next, as we noted in the introduction, reading the pc register reads as the address of the instruction plus 4.

On top of that, the resulting value is then rounded down to the nearest multiple of 4, in order to make it possible to load pc -relative words from memory. The disassembler understands this convention and regenerates the literal constant in the disassembly, saving you the trouble of having to count bytes to look it up.

It appears to be a Windows-specific convention. The assembler automatically emits a literal pool between subroutines, but the immediate offset cannot reach more than about 4KB.

If you have a large function, you may need to help the assembler out by issuing the LTORG pseudo-op to tell the assembler to emit a literal pool immediately. This instruction will load the register R0 with the word at the memory address calculated by adding register leith register R2 shifted left by 2 bits. This is a pre-indexed addressing. This instruction will load the register R0 with the word at the memory address calculated by adding register R1 with register R2 shifted left by 2 bits.

The new address is placed in register R1. This is a post-indexed addressing. This instruction will load the register R0 with the word at memory address contained in register R1.

It will then calculate the new address by adding register R1 with register R2 shifted left by two bits. The new address is placed in register.

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